1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and a testing method therefor. More particularly, the invention relates to a semiconductor integrated circuit device loaded a differential circuit and a CMOS (Complementary Metal-Oxide Semiconductor) circuit and an IDDQ (Quiescent IDD) testing circuit therefor.
2. Description of the Related Art
In a CMOS LSI as a primary semiconductor integrated circuit, demands for higher density and higher speed have been growing. Particularly, a system frequency required for LSI has currently reached in an order of several hundreds MHz. An important task for satisfying such demand is how to improve operation frequency of an LSI output.
As one method for achieving the task, high speed circuits, such as GTL (Gunning Transceiver Logic) circuit, have been proposed. As to the GTL circuit, reference is made to "A CMOS Low-Voltage-Swing Transmission-Line Transceiver" in "ISSCC 92/SESSION 3/HIGH PERFORMANCE CIRCUITS/PAPER WP 3.7 (pp. 58 to 59) reported in IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE, 1992 and "Solid State Products Engineering Council", JEDEC, 1991 and so forth. Most of these circuits achieve high frequency output by making output amplitude smaller. Accordingly, a counterpart LSI input interfacing the LSI output has to be an input circuit corresponding to small amplitude.
FIG. 3 is an illustration showing a construction of an LSI loaded a GTL output circuit a. On an LSI 20, a GTL input circuit b is loaded. On the other hand, in a connection wire 30 connecting a GTL output circuit a and the GTL input circuit b, a terminal resistor R having relatively low resistance value is provided. Through the terminal resistor R, a terminal voltage VT is applied to the connection wire 30.
FIG. 4 is an illustration showing an example of the GTL input circuit b. The GTL input circuit b has a differential circuit construction consisted of P-type MOS transistors T1 and T2. Namely, on a gate of the transistor T1, an input Vin is supplied, and on a gate of the transistor T2, a reference voltage Vref is supplied, respectively. Between a common source of both transistors T1 and T2 and a high potential power source VDD, a P-type MOS transistor T3 is provided. To the gate of the transistor T3, the input Vin is supplied.
As drain loads of both transistors T1 and T2, a current mirror circuit consisted of N-type MOS transistors T4 and T5 is provided. An output Vout is lead from a drain of the transistor T2 via an inverter (generally a CMOS inverter) 1.
In the circuit constructed as set forth above, high frequency operation can be realized easily in comparison with a normal CMOS input circuit. The reason is as follows. A logic signal in the normal CMOS circuit corresponds to VDD (high potential power source voltage of the circuit) at high level, and to a ground level at low level. In contrast to this, the differential input circuit of FIG. 4 is operative at a high level corresponding to a voltage between VDD and Vref, and a low level corresponding to a voltage between Vref and the ground potential to assure stable operation even with a low amplitude input signal.
FIG. 5 shows one example of a relationship of voltage levels at respective parts in the construction of FIG. 3. In the shown example it is assumed that power source voltage VDD=5V, the terminal voltage VT=1.2V and the reference voltage Vref=0.8V. On the other hand, the GTL output circuit is operative between a high level normally being VT and a low level (Vol) normally in a range of 0 &lt;Vol &lt;0.4V. In the circuit construction shown in FIG. 4, a drain output of the transistor T2 applied the reference voltage Vref at the gate thereof is converted into a normal CMOS level by the inverter 1, and thereafter the signal is propagated within the LSI 20.
In the circuit of CMOS structure, while a through current flows upon variation of the signal, little current may flow in steady state. However, when a faulty portion is present in an internal circuit of the LSI and a short circuit is formed between the power source or the ground by such faulty portion, a current flows even in the steady state. Accordingly, testing whether failure is caused in an element of the internal circuit of the LSI or not, can be performed by measuring a consumed current in the steady state. This will be referred to as IDDQ test (static current consumption measuring test: Quiescent IDD test), which is new testing method recently introduced for improving failure detection ratio supplementing a function test employing a test pattern.
On the other hand, a differential circuit shown in FIG. 4 is normally constructed to flow a steady-state current. Therefore, in the steady state (static state) of the LSI, the current may flow in spite of the fact that the LSI operates normally. Therefore, a differential circuit having a circuit construction as shown in FIG. 6 can be considered. Namely, an enabling signal Ven is supplied to the gate of the P-type transistor T3 in the circuit of FIG. 4, and, by providing N-type transistor T6 between the drain of the transistor T2 and the ground, the enabling signal Ven is supplied to the gate of the transistor T6.
In the construction set forth above, by setting the enabling signal Ven at high level, the steady-state current can be cut. However, at this time, the output Vout is fixed at high level irrespective of the value of the input Vin. In a current cut state, IDDQ test can not be implemented by an optimal IDDQ test pattern.
In the conventional CMOS LSI loaded the differential circuit, it has not been possible to perform effective IDDQ test.